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An efficient neural cell architecture for spiking neural networks

Research Abstract

Neurons in a Spiking Neural Network (SNN) communicate using electrical pulses or spikes. They fire or trigger conditionally, and learning is sensitive to such triggers' timing and duration. The Leaky Integrate and Fire (LIF) model is the most widely used SNN neuron model. Most existing LIF-based neurons use a fixed spike frequency, which prevents them from attaining near-optimal accuracy. A research challenge is to design energy and area-efficient SNN neural cells that provide high learning accuracy and are scalable. Recently, the idea of tuning the spiking pulses in SNN was proposed and found promising. This work builds on the pulse-tuning idea by proposing an area and energy-efficient, stable, and reconfigurable SNN cell that generates spikes and reconfigures its pulse width to achieve near-optimal learning. It auto-adapts spike rate and duration to attain near-optimal accuracies for various SNN applications. The …

Research Authors
Kasem Khalil, Ashok Kumar, Magdy Bayoumi
Research Date
Research Department
Research Journal
IEEE Open Journal of the Computer Society
Research Member
Research Website
https://ieeexplore.ieee.org/abstract/document/10972324
Research Year
2025

A Lightweight Hybrid Random Number Generator With Dynamic Entropy Injection

Research Abstract

This paper presents a lightweight hybrid random number generator (HRNG), implemented and evaluated on a Field-Programmable Gate Array (FPGA). The proposed design enhances security and randomness by synergizing jitter and metastability using a feedforward topology, which achieves a near-perfect Shannon entropy. Moreover, it is validated using three distinct entropy metrics, guaranteeing statistically robust random numbers for security-sensitive applications. In addition to entropy evaluations, this design is also rigorously analyzed using multiple industry-standard randomness test suites. Beyond the FPGA implementation, this work presents performance metrics, including area utilization, power consumption, maximum frequency, and energy usage per random bit, which are synthesized across three different technology nodes in Synopsys Design Compiler (SDC). All of the results from the FPGA and the …

Research Authors
Sonia Akter, Shelby Williams, Prosen Kirtonia, Magdy Bayoumi, Kasem Khalil
Research Date
Research Department
Research Journal
IEEE Open Journal of Circuits and Systems
Research Member
Research Website
https://ieeexplore.ieee.org/abstract/document/11106931
Research Year
2025
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