This paper demonstrates a new technique to reduce the comparator delay dispersion caused by variable input overdrive. In the proposed technique, the conventional comparator circuit is modified by adding a variable driving-current block (VDCB) which is used such that it supplies the output node of the differential amplifier with a current that is inversely proportional with the level of input signal. Therefore the overdrive- caused delay dispersion is effectively reduced. The technique incurs small area overhead (only three transistors) compared with the previous works. The proposed circuit is implemented in 45nm technology. The effect of process variation on the performance of the proposed technique is studied by simulation. The results show that the overdrive-related propagation delay dispersion of the proposed technique is 26% of its counterpart in the conventional comparator for an input frequency up to 500MHz. The power consumption is 220 ?W at 200MHz.

This work presents the design and performance of a 10Gbit/s transimpedance amplifier (TIA) implemented in a 40nm CMOS technology. The introduced TIA uses an inverter with active common-drain feedback (ICDF-TIA). The TIA is followed by a two-stage differential amplifier and a 50Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows an optical sensitivity of −19dBm for a BER= 10−12. The transimpedance amplifier achieves a transimpedance gain of 47dBΩ, 8GHz bandwidth with 0.45pF total input capacitance for the photodiode, ESD protection and input PAD. The TIA occupies 0.0002mm2 whereas the complete optical receiver occupies a chip area of 0.16mm2. The power consumption of the TIA is only 2mW and the complete chip dissipates 16mW for a 1.1V single supply voltage. The complete optical receiver has a 58dBΩ transimpedance gain and 7GHz bandwidth.

This work presents the design and performance of a 2.5Gbit/s transimpedance amplifier (TIA) for optical receivers implemented in a 40nm CMOS technology. The TIA is based on an inverting voltage amplifier with a shunt feedback resistor using noise cancelling technique to reduce the input noise. The TIA is followed by two stages of differential limiting amplifiers and the last stage is a 50Ω differential output driver to provide an interface to the measurement setup. The TIA shows a post layout simulated optical sensitivity of −25dBm for a BER= 10−12 and an optical power dynamic range of 25dB. The complete chip achieves a transimpedance gain of 79.5dBΩ, 1.5GHz bandwidth and occupies a chip area of 0.16mm2. The power consumption of the TIA is only 4.5mW and the complete chip dissipates 15mW for a 1.1V single supply voltage.

The presented work describes a plastic optical fiber receiver for gigabit transmission using a resonant cavity light emitting diode (RC-LED). The integrated optical receiver is realized in 0.6μm BiCMOS technology. The main novelty of the presented design is the integration of the equalizer with the optical receiver. A large area Si photodiode is integrated with the optical receiver. The design combines a TIA, equalizer and post amplifier stage followed by a 50 Ω output driver. To minimize power supply noise and substrate noise, a fully differential design is used. A dummy TIA provides a symmetrical input signal reference and a control loop is used to compensate the offset levels. The total transimpedance of the complete receiver chain is in the range of 85dBΩ. The value of the DC gain and the corner frequency of the equalizer can be adapted via an external control voltage to adapt the design to different SI-POF lengths and RC-LED limited bandwidths. The optical receiver operates at a 3.3 V single power supply and the total current consumption is 31mA. The presented optical receiver succeeded to equalize the low-bandwidth transmission system (RC-LED and 50m POF). A data rate of 1Gbit/s can be transmitted over 50m SI-POF with a sensitivity of -13dBm at BER of 10-9