An Efficient Technique for Generating Minimum Test sets for General Tree Logic Circuits

Faculty of Engineering

Assiut University

An Efficient Technique for Generating Minimum Test sets for General Tree Logic Circuits

Research Authors
S. A. Ali and A. Homaifar
Research Member
Samia Abd El-Fattah Ali Hassan
Research Department
Electrical Engineering Department
Research Year
0
Research Journal
International Journal of Electronics
Research Rank
1