Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow

Faculty of Engineering

Assiut University

Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow

Research Authors
M. Abbas, M. Ikeda and K. Asada
Research Member
Mohammed Abbas Abdelrady Abdelhamed
Research Department
Electrical Engineering Department
Research Year
2006
Research Journal
Proceedings of DDECS06, Czech Republic, Prague