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A switched-capacitor delay line with self-equalizing sample-and-hold

Research Authors
M.M. Doss and R. Unbehauen,
Research Member
Research Department
Research Year
1988
Research Journal
International Journal of Electronics
Research Vol
vol. 64, No. 6
Research Rank
1
Research_Pages
pp. 929-933
Research Abstract

A simple SC delay line using a three-phase clock is described. The new circuit uses a reduced number of op amps. A circuit for correcting the amplitude deviation arising from the sample-and-hold effect is used. Unlike previous circuits this circuit does not affect the group-delay of the delay line. An example for a 10 µs delay line in the frequency range 0 to 250 kHz is given.