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In the study, the effect of nano ferric oxide (Fe2O3) modification was investigated to improve the rheological properties of bitumen and mechanical properties of Hot Mix Asphalt (HMA). Rutting potential and non-recoverable compliance (Jnr) were determined after subjecting modified bitumen to short-term and long-term aging. Multiple Stress Creep Recovery (MSCR) test was conducted to evaluate Jnr of bitumen and performance grade. Low temperature stiffness and flexural properties of modified bitumen were also determined. Indirect Tensile Strength (ITS) and Tensile Strength Ratio (TSR) of HMA modified with nano Fe2O3 was determined. Rutting was also determined by Hamburg Wheel Tracking Device (HWTD) for HMA modified with nano Fe2O3. Solar reflection was measured on HMA modified with nano Fe2O3. Results showed that, the nano Fe2O3 improved the rutting potential and non-recoverable compliance. Maximum rutting performance was observed by 5% Fe2O3 modified bitumen. The non-recoverable compliance and the rutting resistance have related. Modified HMA samples have higher strength value than reference sample. Nano Fe2O3 modification of HMA was provided resistance against moisture damage. 1% Fe2O3 modified HMA has the highest rutting resistance with the maximum 6 mm rut depth. Heat islands were increased by nano Fe2O3 modification.

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Built heritage forms a unique asset by expressing the richness and diversity of our history, possessing vast amounts of information that varies from factual and explicit, to more tacit and embedded. Tacit knowledge of built heritage is typically more challenging to communicate to visitors in understandable and engaging ways due to its implicit and abstract character. Therefore, we investigate how built heritage information can be disclosed via simultaneous and integrated physical and digital means, and how this information can be communicated to visitors in more engaging, educational and meaningful ways. In this thesis we present the approach of "Phygital Heritage", which entails how heritage information can be disclosed via simultaneous and integrated physical and digital means. We hypothesize that this approach forms a potential medium for more engaging and meaningful communication of heritage information to a broader public. It even enables heritage visitors to appreciate heritage in more experiential ways, and to raise community awareness about heritage assets. Through a set of in-the-wild studies, in which interactive phygital prototypes were designed and deployed in real-world heritage and museum environments, we explore how the seamless integration of digital technology into physical reality facilitates the communication of built heritage information to museum visitors and how it affects user engagement. In Saqqara Entrance Colonnade, through a between-group comparative study in a real-world museum context, we examined how the tangible characteristics of an interactive museum prototype influence how visitors understand tacit knowledge of built heritage; In Nimrud Relief, through a field study in a real-world museum environment, we investigated how an augmented reality experience impacts the architectural contextualization of an isolated artifact from the Nimrud palace in Iraq; In Graethem Chapel, through an in-the-wild study, we investigated how an in-situ interactive projection mapping enables the communication of the spatiotemporal transformation of a medieval chapel that occurred during the last 850 years; and In Neferirtenef Tomb-Chapel, through a field study in a real-world museum environment, we investigated how a tangible gamification installation supports informal cultural learning of young museum visitors and how it encourages collaboration among them. In summary, this thesis contributes to the knowledge about the communication of built heritage information by demonstrating how this information can be disclosed via simultaneous and integrated physical and digital means, enabling the broader public to appreciate heritage in more experiential ways.

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This paper presents an approach using gm/ID methodology for the design of the regulated cascode circuit (RGC) transimpedance amplifier (TIA) for optical receivers. The framework uses lookup tables produced using the gm/ID methodology to define the sizing of the transistors needed to reach the required specifications. The framework has the advantage of setting limits on the design space using intuitive equations derived from the circuit analyses. This gives insight into the effect of changing the value of different circuit parameters on the resulting design while decreasing the time to reach the desired design. The framework gives the flexibility to minimize the DC power consumption or the total input referred noise. The framework is implemented in a 130 nm CMOS process with a 1.5 V supply voltage producing two different designs. Both designs met the required specifications while optimizing power consumption

This paper presents an approach using gm/ID methodology for the design of the regulated cascode circuit (RGC) transimpedance amplifier (TIA) for optical receivers. The framework uses lookup tables produced using the gm/ID methodology to define the sizing of the transistors needed to reach the required specifications. The framework has the advantage of setting limits on the design space using intuitive equations derived from the circuit analyses. This gives insight into the effect of changing the value of different circuit parameters on the resulting design while decreasing the time to reach the desired design. The framework gives the flexibility to minimize the DC power consumption or the total input referred noise. The framework is implemented in a 130 nm CMOS process with a 1.5 V supply voltage producing two different designs. Both designs met the required specifications while optimizing power consumption

This paper presents an approach using gm/ID methodology for the design of the regulated cascode circuit (RGC) transimpedance amplifier (TIA) for optical receivers. The framework uses lookup tables produced using the gm/ID methodology to define the sizing of the transistors needed to reach the required specifications. The framework has the advantage of setting limits on the design space using intuitive equations derived from the circuit analyses. This gives insight into the effect of changing the value of different circuit parameters on the resulting design while decreasing the time to reach the desired design. The framework gives the flexibility to minimize the DC power consumption or the total input referred noise. The framework is implemented in a 130 nm CMOS process with a 1.5 V supply voltage producing two different designs. Both designs met the required specifications while optimizing power consumption